This paper proposes a novel implementation of Ternary Decoder using CMOS DPL (Double Pass Logic) Binary logic gates , in standard digital CMOS technology. The physical design of the circuits is simulated and tested with Micro-Cap 10 SPICE simulator. The Proposed decoder circuit could be embedded in digital CMOS VLSI design architectures. The Proposed decoder circuit will be the basic circuit to create other Ternary Logic Circuits like Ternary Logic Gates, Ternary Memory, Half Adder, Full Adder, Multiplier, Multiplexer and others. The simulation results demonstrate the merits of the approach in terms of reduced number of transistors by 25% therefore will reduce energy consumption.